PLD design software
When PLDs such as PALs had only a thousand or fewer programmable connections, it was possible to do the design by hand. A chart provided by the manufacturer was used to mark in the desired connections and then the fuse numbers were set up in the programmer using data editing commands. Since the 80's and 90's design software has become the only way, because device sizes just got too big to keep track of the details. Devices are now approaching a billion transistors, with millions of programmable connections. The use of software involves coding the design in a Hardware Decription Language (a HDL). Using a HDL brings all the benefits of abstraction, macros and modules into the development cycle.
The following expandible sections show a little bit about the major Hardware Design Languages that are specific to, or used to design for PLDs (roughly in chronological order). In each case I code the same simple example function (a "D" flip-flop with an AND term feeding its D input), as in the image to the left:
Not entered is STAPL. I just haven't had any exposure to it. If anybody wants to add an
equivalent paragraph or two about it, notify me via the contacts page 
and I'll give full credit!
1 PALASM |
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CHIP FF PAL16L8 PIN 1 CLOCK PIN 2 A PIN 3 B PIN 14 Q EQUATIONS Q := A*B
This was the first major software tool. MMI brought it out with their PALs, hence the name. It can still be found in University courses, and where small parts are all that are being used. There was also PLEASM for designing with PROMs as logic elements. (MMI had a series of registered PROMs which they called Programmable Logic Elements). The simple example, coded in PALASM, shows the 1970's origin of the language, I think.
2 CUPL |
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Device 16L8; pin 1 = CLOCK; pin 2 = A; pin 3 = B; pin 14 = Q; Q.CK = CLOCK; Q = A & B;
This is a language developed by Logical Devices. It is still used for smaller PLDs. Atmel is the main PLD manufacturer that uses it. The simple example of a 'D' flip-flop is shown in CUPL here (probably not too complete!):
3 ABEL |
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module ff ffchip device 'p16L8'; CLOCK pin 1; A,B pin 2,3; Q pin 14 istype 'reg_d'; EQUATIONS Q.CK = CLOCK; Q := A*B; end;
ABEL stands for "Advanced Boolean Equation Language." It was developed by Data I/O. It is still very much in use for small and medium PLDs.
4 AHDL |
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Title " "; Subdesign ff ( Clock: input ; A: input ; B: input ; Q: output ; ) Begin (Y_1, Y_0) = A and B; end ;
An Altera-specific language which looks a bit like Abel and a bit like VHDL.
5 VHDL |
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entity ff is port (a,b,clk: in
std_logic; q: out std_logic);
end ff;
architecture ff of ff is begin
process (clk,a,b)
begin
if (clk'event and clk ='1') then
q<= a and b;
end if;
end process;
end ff;
A nested acronym: the V itself stands for an acronym, VHSIC, which is Very High Speed Integrated Circuit. The rest of the acronym should be obvious if you have been following along! VHDL is big. It came out of the US military's need to have a common way of specifying, designing and testing high speed ICs. This legacy is evident in that there is some similarity to Ada, which of course, has a similar government background.
The simple example of a flip-flop is shown at right. The example is not complete since there are neither signal declarations, library invocations, nor package or pin definitions. This is coded as a behavioural description: VHDL can also be coded as structural (gate inputs and outputs simply wired together) or as dataflow (which can be considered a different form of behavioural description).
6 Verilog |
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module ff (clk, a, b, q);
input clk, a, b;
output q;
always @(posedge clk)
q <= a && b;
end
endmodule
Similar in many respects to VHDL, Verilog is another modern HDL. Many tool sets support both VHDL and Verilog because both have their adherents.
Tip: If you want to see all of the entries, just click on the '<' on the first item.
Comments, corrections via the contacts page please.